The present invention relates to electronic devices, and, more particularly, to integrated circuits including component delay lines and methods of delay generation.
Clocked digital systems often need multiple clock phases for fine timing control, and such phases can be flexibly generated by use of delay lines to simply defining clock phases as delayed versions of the system clock. Similarly, analog systems can use tapped delay lines for performing discrete convolutions and similar operations. Indeed, a simple ring oscillator made of an inverter with a delay line feedback will have a frequency equal to the inverse of the delay.
Circuitry requiring a delay line will often be connected to an external delay line: monolithic multitap delay lines with programmable delays are available. For example, the DS1020 manufactured by Dallas Semiconductor Corporation provides programmable delays from 10 nsec to over 500 nsec. However, for circuitry that is integrated into a single chip, the use of external delay lines becomes unreliable, expensive, requires chip pins for connection, and the delay accuracy does not scale. Thus there is a need for an accuracy-scalable delay line that may be fabricated as part of a digital integrated circuit.
Further, semiconductor device speed depends upon various factors, and not uncommonly there is a speed variation of four-to-one for supposedly identically manufactured integrated circuits operating under differing conditions. External delays lines cannot fully compensate for such variations, and there is a need for operating condition compensation within delay lines.
An alternative to delay lines for granularizing a digital system's clock is the use of a phase locked loop to multiply the clock frequency. A phase locked loop can be formed as part of an integrated circuit, but has the problems of cumbersome integration due to the voltage controlled oscillator and a lock-in time for any nontrivial frequency change. Additionally, most digital integrated circuits offerings, such as standard cells and gate arrays, do not offer voltage controlled oscillator building blocks.
The present invention provides embodiments with a speed calibration for a circuit using delay elements and then applies the calibration to control other delay lines made of analogous delay elements to provide device-speed independent delays.